The combination of continuing advances in technology and reduced production costs have led to a proliferation of electronic devices that incorporate or use advanced digital circuits. These electronic devices include desktop computers, laptop computers, hand-held computing devices, such as Personal Digital Assistants (PDAs) and hand-held computers, as well as cellular telephones, printers, digital cameras, facsimile machines, and household and business appliances, among others. The digital circuits included in these electronic devices may be used to provide the basic functionality of the electronic devices or may be used to provide additional, desirable features.
It is desired to produce circuit designs for such devices that are reliable, cost-effective and that provide adequate performance for the application. The cost of a circuit is typically measured in terms of its silicon area and may be estimated from the number of components (functional units, registers, wires, etc.) in the circuit. The performance of the circuit can be expressed as a combination of several metrics, including throughput (the number of tasks executed per clock cycle), latency (the number of clock cycles to complete a single task) and clock speed.
Programmatic techniques have been developed for synthesizing such circuits and their designs. Generally, the process takes a functional specification for the design (e.g., written in a high-level software language, such as C) and produces a hardware circuit with the same functionality as the functional specification.
The functional specification for the design undergoes two design phases: architectural synthesis and physical synthesis. During architectural synthesis, the code is analyzed for dependencies (i.e. where results of an operation are required as input to one or more other operations). Based on the analysis, optimizing transformations are performed on the code (e.g., the operations are reordered) and the operations are mapped to high-level hardware elements and scheduled to occur at specific times. In other words, code from the program is converted into compute devices (such as multipliers and adders) to perform the program's computations, memory devices (such as registers and RAM) to store the program's data, and control devices (such as finite-state machines and micro-controllers) to control execution of the program's instructions. The resulting hardware circuit is typically specified at the register-transfer level (RTL), which is a clock cycle-level structural description of the hardware using high-level hardware elements.
During physical synthesis, the high-level hardware elements are synthesized into low-level hardware elements, such as gates or transistors. The low-level hardware elements are physically arranged and interconnections between the elements are routed. In other words, the RTL specification is mapped onto a physical hardware circuit, such as a field-programmable gate array (FPGA) or other type of target hardware.
Often, it is discovered during the physical synthesis phase that the resulting design does not meet all constraints, such as timing, performance or interconnection routability requirements. When this occurs, a time-consuming manual process is used in which critical paths in the design are discovered and corrected and, then, the circuit is re-synthesized. Correcting all of the critical paths can take several design iterations.
Therefore, what is needed is an improved technique for digital circuit synthesis. What is further needed is such a technique in which timing and routability considerations are taken into account during architecture synthesis so as to reduce the need for manual corrective action during physical synthesis. It is toward these ends that the present invention is directed.